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| KS8721B/BT Micrel KS8721B/BT 2.5V 10/100BasTX/FX MII Physical Layer Transceiver Rev. 2.2 General Description Operating at 2.5 volts to meet low voltage and low power requirements, the KS8721B/BT is a 10BaseT/100BaseTX/ FX Physical Layer Transceiver, which provides an MII to transmit and receive data. It contains the 10BaseT Physical Medium Attachment (PMA), Physical Medium Dependent (PMD), and Physical Coding Sub-layer (PCS) functions. Moreover, the KS8721B/BT has on-chip 10BaseT output filtering, which eliminates the need for external filters and allows a single set of line magnetics to be used to meet requirements for both 100BaseTX and 10BaseT. The KS8721B/BT can automatically configure itself for 100 or 10 Mbps and full or half duplex operation, using on-chip AutoNegotiation algorithm. It is an ideal choice of physical layer transceiver for 100BaseTX/10BaseT applications. Data sheets and support documentation can be found on Micrel's web site at www.micrel.com. Features * Single chip 100BaseTX/100BaseFX/10BaseT physical layer solution * 2.5V CMOS design, power consumption <200mW (excluding output driver current ) * Fully compliant to IEEE 802.3u standard * Supports Media Independent Interface (MII) and Reduced MII (RMII) * Supports 10BaseT, 100BaseTX and 100BaseFX with Far_End_Fault Detection * Supports power down mode and power saving mode * Configurable through MII serial management ports or via external control pins * Supports auto-negotiation and manual selection for 10/100Mbps speed and full/half-duplex mode * On-chip built-in analog front end filtering for both 100BaseTX and 10BaseT Functional Diagram TX+ TX- Transmitter 10/100 Pulse Shaper NRZ/NRZI MLT3 Encoder 4B/5B Encoder Scrambler Parallel/Serial Parallel/Serial Manchester Encoder RX+ RX- Adaptive EQ Base Line Wander Correction MLT3 Decoder NRZI/NRZ Clock Recovery 4B/5B Decoder Descrambler Serial/Parallel MII/RMII Registers and Controller Interface Auto Negotiation 10BaseT Receiver Power Down or Saving XI XO PLL PWRDWN Manchester Decoder Serial/Parallel TXD3 TXD2 TXD1 TXD0 TXER TXC TXEN CRS COL MDIO MDC RXD3 RXD2 RXD1 RXD0 RXER RXDV RXC LINK LED Driver COL FDX SPD Micrel, Inc. * 1849 Fortune Drive * San Jose, CA 95131 * USA * tel + 1 (408) 944-0800 * fax + 1 (408) 944-0970 * http://www.micrel.com August 2003 1 KS8721B/BT KS8721B/BT Micrel Features (continued) * LED outputs for link, activity, full/half duplex, collision and speed * Supports back to back, FX to TX for media converter applications * Supports MDI/MDI-X auto crossover * 2.5V/3.3V tolerance on I/O * Commercial temperature range: 0C to +70C * Industrial temperature range: -40C to +85C * Available in 48-pin SSOP and TQFP Ordering Information Part Number KS8721B KS8721BI KSZ8721B KS8721BT KSZ8721BT Temperature Range 0C to +70C -40C to +85C 0C to +70C 0C to +70C 0C to +70C Package 48-Pin SSOP 48-Pin SSOP 48-Pin SSOP Lead Free 48-Pin TQFP 48-Pin TQFP Lead Free KS8721B/BT 2 August 2003 KS8721B/BT Micrel Revision History Revision 1.0 2.0 Date 2/29/02 4/01/02 Summary of Changes Document Origination (Preliminary) Update timing Spec from page 33 to page 37 Change Revision ID from 1000 to 1001 Add new control register bit, Control Register 0 Bit 0, to control transmit enable/disable Add 8h register map on the table Editorial Change on FXSD/FXEN pin34 Change on duplex pin38 0=half and 1=full duplex Change on the 10BT MII transmit timing 1.0us to 2.5us and Tlat 2.5us to 4BT Add the TEST description mode on pin26 Add part number ordering information & remove pinout diagram Edited pin description on the IO cloumn Change the company logo, disclaimer, & contact info Editorial changes on Stapping option description Change on Register0h bit0, 1=disable and 0=enable Add remote fault register4h bit13. Add normal operating condition table & Thermal data for SSOP48 table Add Reset Timing table & Transformer Lists Add 48 TQFP pinout diagram & RMII AC Charateristics Add ordering info for 48 Pin TQFP package, KS8721B/BTI industrial temperature, KSY8721B/KSY8721BT environmentally friendly part number Change part number from KS8721B to KS8721B/BT. Change ordering info. from "KSY" to "KSZ" for lead free. Change pin name from RMII_LPBK to RMII_BTB Convert to new format. 2.1 1/31/03 2.2 8/29/03 August 2003 3 KS8721B/BT KS8721B/BT Micrel Table Of Contents Pin Description ............................................................................................................................................................ 6 Strapping Option ......................................................................................................................................................... 9 Pin Configuration ...................................................................................................................................................... 10 Introduction ........................................................................................................................................................... 11 100BaseTX Transmit ........................................................................................................................................... 11 100BaseTX Receive ............................................................................................................................................ 11 PLL Clock Synthesizer ......................................................................................................................................... 11 Scrambler/De-scrambler (100BaseTX only) ........................................................................................................ 11 10BaseT Transmit ............................................................................................................................................... 11 10BaseT Receive ................................................................................................................................................ 11 SQE and Jabber Function (10Base only) ............................................................................................................ 11 Auto-Negotiation .................................................................................................................................................. 11 MII Management Interface ................................................................................................................................... 12 MII Data Interface ................................................................................................................................................ 12 Transmit Clock ............................................................................................................................................. 12 Receive Clock .............................................................................................................................................. 12 Transmit Enable ........................................................................................................................................... 12 Receive Data Valid ...................................................................................................................................... 12 Error Signals ................................................................................................................................................ 12 Carrier Sense ............................................................................................................................................... 12 Collision ....................................................................................................................................................... 13 RMII Signal Definition .......................................................................................................................................... 13 Reference Clock .................................................................................................................................................. 13 Carrier Sense/Receive Data Valid ....................................................................................................................... 13 Receive Data ....................................................................................................................................................... 13 Transmit Enable ................................................................................................................................................... 13 Transmit Data ...................................................................................................................................................... 14 Collision Detection ............................................................................................................................................... 14 RX_ER ........................................................................................................................................................... 14 RMII AC Characteristics ...................................................................................................................................... 14 Auto Crossover (Auto MDI/MDI-X) ...................................................................................................................... 15 Power Management ............................................................................................................................................. 16 100BT FX Mode ................................................................................................................................................... 16 Media Converter Option ....................................................................................................................................... 16 Register Map ........................................................................................................................................................... 17 Register 0h: Basic Conrol ................................................................................................................................... 17 Register 1h: Basic Status .................................................................................................................................... 18 Register 2h: PHY Identifier 1 .............................................................................................................................. 18 Register 3h: PHY Identifier 2 .............................................................................................................................. 18 Register 4h: Auto-Negotiation Advertisement ..................................................................................................... 18 Register 5h: Auto-Negotiation Link Partner Ability .............................................................................................. 18 Register 6h: Auto-Negotiation Expansion ........................................................................................................... 19 Register 7h: Auto-Negotiation Next Page ........................................................................................................... 19 Register 8h: Link Partner Next Page Ability ........................................................................................................ 19 Register 15h: RXER Counter .............................................................................................................................. 20 Register 1bh: Interrupt Control/Status Register .................................................................................................. 20 Register 1fh: 100BaseTX PHY Controller ........................................................................................................... 20 KS8721B/BT 4 August 2003 KS8721B/BT Absolute Maximum Ratings ..................................................................................................................................... Operating Ratings ..................................................................................................................................................... Electrical Characteristics .......................................................................................................................................... Timing Diagrams ....................................................................................................................................................... Selection of Isolation Transformers ........................................................................................................................ Selection of Reference Crystals ............................................................................................................................... Package Outline and Dimensions ............................................................................................................................ Micrel 22 22 22 24 30 30 31 August 2003 5 KS8721B/BT KS8721B/BT Micrel Pin Description Pin Number 1 2 3 Pin Name MDIO MDC RXD3/ PHYAD1 Type(Note 1) I/O I Ipd/O Pin Function Management Interface (MII) Data I/O: This pin requires an external 10K pull-up resistor. Management Interface (MII) Clock Input: This pin is synchronous to the MDIO data interface MII Receive Data Output: RXD [3..0], these bits are synchronous with RXCLK. When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII. RXD [3..0] is invalid when RXDV is de-asserted. The pull-up/pull-down value is latched as PHYADDR [1] during reset. See "Strapping Options" section for details. MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [2] during reset. See "Strapping Options" section for details. MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [3] during reset. See "Strapping Options" section for details. MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [4] during reset. See "Strapping Options" section for details. Digital IO 2.5 /3.3V tolerance power supply. Ground. MII Receive Data Valid Output: The pull-up/pull-down value is latched as pcs_lpbk during reset. See "Strapping Options" section for details. MII Receive Clock Output: Operating at 25MHz = 100Mbps, 2.5MHz = 10Mbps. MII Receive Error Output: The pull-up/pull-down value is latched as ISOLATE during reset. See "Strapping Options" section for details. Ground. Digital core 2.5V only power supply. MII Transmit Error Input. MII Transmit Clock Output: RMII Reference Clock Input. MII Transmit Enable Input MII Transmit Data Input MII Transmit Data Input MII Transmit Data Input MII Transmit Data Input MII Collision Detect Output: The pull-up/pull-down value is latched as RMII select during reset. See "Strapping Options" section for details. Digital IO 2.5/3.3V tolerance power supply. 4 5 6 7 8 9 RXD2/ PHYAD2 RXD1/ PHYAD3 RXD0/ PHYAD4 VDDIO GND RXDV/ CRSDV/ PCS_LPBK RXC RXER/ISO GND VDDC TXER TXC/ REFCLK TXEN TXD0 TXD1 TXD2 TXD3 COL/RMII VDDIO Ipd/O Ipd/O Ipd/O Pwr GND Ipd/O 10 11 12 13 14 15 16 17 18 19 20 21 24 Note 1. O Ipd/O GND Pwr Ipd Ipu/O Ipd Ipd Ipd Ipd Ipd Ipd/O Pwr Pwr = power supply GND = ground I = input O = output I/O = bi-directional Gnd = ground Ipu = input w/ internal pull-up Ipd = input w/ internal pull-down Ipd/O = input w/ internal pull-down during reset, output pin otherwise Ipu/O = input w/ internal pull-up during reset, output pin otherwise PU = strap pin pull-up PD = strap pin pull-down NC = No connect KS8721B/BT 6 August 2003 KS8721B/BT Pin Number 25 22 Pin Name INT#/ PHYAD0 CRS/ RMII_BTB GND LED0/TEST Type(Note 1) Ipu/O Ipd/O Pin Function Micrel Management Interface (MII) Interrupt Out: Latched as PHYAD[0] during power up /reset. See "Strapping Options" section for details. MII Carrier Sense Output: The pull-up/pull-down value is latched as RMII BTB during reset when RMII mode is selected. See "Strapping Options" section for details. Ground. Link/Activity LED Output: Lnk/Act No Link Link Act Pin State H L -- LED Definition "off" "on" "Toggle" 23 26 GND Ipu/O The external pull-down enable test mode and only used for the factory test. 27 LED1/ SPD100/ noFEF Ipu/O Speed LED Output: Latched as SPEED (Register 0, bit 13) during power-up/reset. See "Strapping Options" section for details. Speed 10BT 100BT 28 LED2/ DUPLEX Ipu/O Pin State H L LED Definition "off" "on" Full-duplex LED Output: Latched as DUPLEX (register 0h, bit 8) during power-up/ reset. See "Strapping Options" section for details. Duplex Half Full Pin State H L LED Definition "off" "on" 29 LED3/ NWAYEN Ipu/O Collision LED Output: Latched as ANEG_EN (register 0h, bit 12) during power-up/ reset. See "Strapping Options" section for details. Collison No Collision Collision Pin State H L LED Definition "off" "on" 30 31 32 33 34 35 36 Note 1. PD# VDDRX RXRX+ FXSD/FXEN GND GND Ipu Pwr I I Ipd/O GND GND Power Down. 1 = Normal operation, 0=Power down, Active low. Analog 2.5V power supply. Receive Input: Differential receive input pins for FX, 100BaseTX or 10BaseT. Receive Input: Differential receive input pin for FX, 100BaseTX or 10BaseT. Fiber Mode Enable / Signal Detect in Fiber Mode. If FXEN = 0, FX mode is disable. The default is "0". See "100BT FX Mode" section for more details. Ground. Ground. Pwr = power supply GND = ground I = input O = output I/O = bi-directional Ipu = input w/ internal pull-up Ipd = input w/ internal pull-down Ipd/O = input w/ internal pull-down during reset, output pin otherwise Ipu/O = input w/ internal pull-up during reset, output pin otherwise PU = strap pin pull-up PD = strap pin pull-down NC = No connect August 2003 7 KS8721B/BT KS8721B/BT Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 Note 1. Micrel Pin Name REXT VDDRCV GND TXTX+ VDDTX GND GND XO XI VDDPLL RST# Type(Note 1) I Pwr GND O O Pwr GND GND O I Pwr Ipu Pin Function External resistor (6.49k) connects to REXT and GNDRX. Analog 2.5V power supply. Ground Transmit Outputs: Differential transmit output for 100BaseTX/FX or 10BaseT. Transmit Outputs: Differential transmit output for FX, 100BaseTX/FX or 10BaseT. Transmitter 2.5V power supply. Ground. Ground. XTAL feedback: Used with XI for Xtal application. Crystal Oscillator Input: Input for a crystal or an external 25MHz clock Analog PLL 2.5V power supply. Chip Reset: Active low, minimum of 50s pulse is required Pwr = power supply GND = ground I = input O = output I/O = bi-directional Ipu = input w/ internal pull-up Ipd = input w/ internal pull-down Ipd/O = input w/ internal pull-down during reset, output pin otherwise Ipu/O = input w/ internal pull-up during reset, output pin otherwise PU = strap pin pull-up PD = strap pin pull-down NC = No connect KS8721B/BT 8 August 2003 KS8721B/BT Micrel Strapping Options(Note 1) Pin Number 6,5, 4,3 25 9 11 21 22 27 Pin Name PHYAD[4:1]/ RXD[0:3] PHYAD0/ INT# PCS_LPBK/ RXDV ISO/RXER RMII/COL RMII_BTB CRS SPD100/ No FEF/ LED1 DUPLEX/ LED2 NWAYEN/ LED3 PD# Type(Note 2) Ipd/O Ipu/O Ipd/O Ipd/O Ipd/O Ipd/O Ipu/O Enables PCS_LPBK mode at power-up/reset. PD (default) = Disable, PU = Enable. Enables ISOLATE mode at power-up/reset. PD (default) = Disable, PU = Enable. Enables RMII mode at power-up/reset. PD (default) = Disable, PU = Enable. Enable RMII_BTB mode at power-up/reset. PD (default) = Disable, PU = Enable. Latched into Register 0h bit 13 during power-up/reset. PD = 10Mbps, PU (default) = 100Mbps. If SPD100 is asserted during power-up/reset, this pin also latched as the Speed Support in register 4h. (If FXEN is pulled up, the latched value 0 means no Far_End _Fault.) Latched into Register 0h bit 8 during power-up/reset. PD = Half duplex, PU (default) = Full duplex. If Duplex is pulled up during reset, this pin also latched as the Duplex support in register 4h. Nway (auto-negotiation) Enable. Latched into Register 0h bit 12 during power-up/ reset. PD = Disable Auto-Negotiation, PU (default) = Enable Auto-Negotiation. Power Down Enable. PU (default) = Normal operation, PD = Power down mode. Description PHY Address latched at power-up/reset. The default PHY address is 00001. 28 Ipu/O 29 30 Note 1. Note 2. Ipu/O Ipu Strap-in is latched during power-up or reset. Ipu = input w/ internal pull-up Ipd = input w/ internal pull-down Ipd/O = input w/ internal pull-down during reset, output pin otherwise Ipu/O = input w/ internal pull-up during reset, output pin otherwise PU = strap pin pull-up PD = strap pin pull-down August 2003 9 KS8721B/BT KS8721B/BT Micrel Pin Configuration MDIO 1 MDC 2 R3D3/PHYAD1 3 RXD2/PHYAD2 4 RXD1/PHYAD3 5 RXD0/PHYAD4 6 VDDIO 7 GND 8 RXDV/PCS_LPBK 9 RXC 10 RXER/ISO 11 GND 12 VDDC 13 TXER 14 TXC/REF_CLK 15 TXEN 16 TXD0 17 TXD1 18 TXD2 19 TXD3 20 COL/RMII 21 CRS/RMII_BTB 22 GND 23 VDDIO 24 48 RST# 47 VDDPLL 46 XI 45 XO 44 GND 43 GND 42 VDDTX RST# VDDPLL X1 X0 GND GND VDDTX TX+ TX-- GND VDDRCV REXT 41 TX+ 40 TX39 GND 38 VDDRCV 37 REXT 36 GND 35 GND 34 FXSD/FXEN 33 RX+ 32 RX31 VDDRX 30 PD# 29 LED3/NWAYEN 28 LED2/DUPLEX 27 LED1/SPD100 26 LED0/TEST 25 INT#/PHYAD0 48 47 46 45 44 43 42 41 40 39 38 37 MDIO MDC RXD3/PHYAD1 RXD2/PHYAD2 RXD1/PHYAD3 RXD0/PHYAD4 VDDIO GND RXDV/PCS_LPBK RXC RXER/ISO GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 VDDC TXER TXC/REF_CLK TXEN TXD0 TXD1 TXD2 TXD3 COL/RMII CRS/RMII_BTB GND VDDIO 36 35 34 33 32 31 30 29 28 27 26 25 GND GND FXSD/FXEN RX+ RX-- VDDRX PD# LED3/NWAYEN LED2/DUPLEX LED1/SPD100 LED0/TEST INT#/PHYAD0 48-Pin SSOP (SM) 48-Pin TQFP (TQ) KS8721B/BT 10 August 2003 KS8721B/BT Micrel Introduction 100BaseTX Transmit The 100BaseTX transmit function performs parallel to serial conversion, NRZ to NRZI conversion, MLT-3 encoding and transmission. The circuitry starts with a parallel to serial conversion, which converts the 25MHz, 4-bit nibbles into a 125 MHz serial bit stream. The incoming data is clocked in at the positive edge of the TXC signal. The serialized data is further converted from NRZ to NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 1% 6.49k resistor for the 1: 1 transformer ratio. It has a typical rise/fall times of 4 ns and complies to the ANSI TP-PMD standard regarding amplitude balance, overshoot and timing jitters. The wave-shaped 10BaseT output driver is also incorporated into the 100BaseTX driver. 100BaseTX Receive The 100BaseTX receive function performs adaptive equalization, DC restoration, MLT-3 to NRZI conversion, data and clock recovery, NRZI to NRZ conversion, and serial to parallel conversion. The receiving side starts with the equalization filter to compensate inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion are a function of the length of the cable, the equalizer has to adjust its characteristic to optimize the performance. In this design, the variable equalizer will make an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. This is an ongoing process and can self adjust against the environmental changes such as temperature variations. The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate effect of base line wander and improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. Finally, the NRZ serial data is converted to 4-bit parallel 4B nibbles. A synchronized 25MHz RXC is generated so that the 4B nibbles is clocked out at the negative edge of RCK25 and is valid for the receiver at the positive edge. When no valid data is present, the clock recovery circuit is locked to the 25MHz reference clock and both TXC and RXC clocks continue to run. PLL Clock Synthesizer The KS8721B/BT generates 125MHz, 25MHz and 20MHz clocks for system timing. An internal crystal oscillator circuit provides the reference clock for the synthesizer. Scrambler/De-scrambler (100BaseTX only) The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. 10BaseT Transmit When TXEN (transmit enable) goes high, data encoding and transmission will begin. The KS8721B/BT will continue to encode and transmit data as long as TXEN remains high. The data transmission will end when TXEN goes low. The last transition occurs at the boundary of the bit cell if the last bit is zero, or at the center of the bit cell if the last bit is one. The output driver is incorporated into the 100Base driver to allow transmission with the same magnetics. They are internally wave-shaped and pre-emphasized into outputs with a typical 2.5V amplitude. The harmonic contents are at least 27dB below the fundamental when driven by an all-ones Manchester-encoded signal. 10BaseT Receive On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 300mV or with short pulse widths in order to prevent noises at the RX+ or RX- input from falsely trigger the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KS8721B/BT decodes a data frame. This activates the carrier sense (CRS) ad RXDV signals and makes the receive data (RXD) available. The receive clock is maintained active during idle periods in between data reception. SQE and Jabber Function (10BaseT only) In 10BaseT operation, a short pulse will be put out on the COL pin after each packet is transmitted. This is required as a test of the 10BaseT transmit/receive path and is called SQE test. The 10BaseT transmitter will be disabled and COL will go high if TXEN is High for more than 20ms (Jabbering). If TXEN then goes low for more than 250ms, the 10BaseT transmitter will be re-enabled and COL will go Low. Auto-Negotiation The KS8721B/BT performs auto-negotiation by hardware strapping option (pin 29) or software (Register 0.12). It will automatically choose its mode of operation by advertising its abilities and comparing them with those received from its link partner whenever auto-negotiation is enabled. It can also be configured to advertise 100BaseTX or 10BaseT in either full- or half-duplex mode (please refer to "Auto-Negotiation" ). The auto-negotiation is disabled in the FX mode. August 2003 11 KS8721B/BT KS8721B/BT Micrel During auto-negotiation, the contents of Register 4, coded in Fast Link Pulse (FLP), will be sent to its link partner under the conditions of power-on, link-loss or re-start. At the same time, the KS8721B/BT will monitor incoming data to determine its mode of operation. Parallel detection circuit will be enabled as soon as either 10BaseT NLP (Normal Link Pulse) or 100BaseTX idle is detected. The operation mode is configured based on the following priority: Priority 1: 100BaseTX, full-duplex Priority 2: 100BaseTX, half-duplex Priority 3: 10BaseT, full-duplex Priority 4: 10BaseT, half-duplex When the KS8721B/BT receives a burst of FLP from its link partner with 3 identical link code words (ignoring acknowledge bit), it will store these code words in Register 5 and wait for the next 3 identical code words. Once the KS8721B/BT detects the second code words, it then configures itself according to above-mentioned priority. In addition, the KS8721B/BT also checks 100BaseTX idle or 10BaseT NLP symbol. If either is detected, the KS8721B/BT automatically configures to match the detected operating speed. MII Management Interface The KS8721B/BT supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input / Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the KS8721B/BT. The MDIO interface consists of the following: * A physical connection including a data line (MDIO), a clock line (MDC) and an optional interrupt line (INTRPT) * A specific protocol that runs across the above-mentioned physical connection and it also allows one controller to communicate with multiple KS8721B/BT devices. Each KS8721B/BT assigned an MII address between 0 and 31 by the PHYAD inputs. * An internal addressable set of fourteen 16-bit MDIO registers. Register [0:6] are required and their functions are specified by the IEEE 802.3 specifications. Additional registers are provided for expanded functionality. The INTPRT pin functions as a management data interrupt in the MII. An active Low or High in this pin indicates a status change on the KS8721B/BT based on 1fh.9 level control. Register bits at 1bh[15:8] are the interrupt enable bits. Register bits at 1bh[7:0] are the interrupt condition bits. This interrupt is cleared by reading Register 1bh. MII Data Interface The data interface consists of separate channels for transmitting data from a 10/100 802.3 compliant Media Access Controller (MAC) to the KS8721B/BT, and for receiving data from the line. Normal data transmission is implemented in 4B Nibble Mode (4-bit wide nibbles). Transmit Clock (TXC): The transmit clock is normally generated by the KS8721B/BT from an external 25MHz reference source at the X1 input. The transmit data and control signals must always be synchronized to the TXC by the MAC. The KS8721B/BT normally samples these signals on the rising edge of the TXC. Receive Clock (RXC): For 100BaseTX links, the receive clock is continuously recovered from the line. If the link goes down, and auto-negotiation is disabled, the receive clock operates off the master input clock (X1 or TXC). For 10BaseT links, the receive clock is recovered from the line while carrier is active, and operates from the master input clock when the line is idle. The KS8721B/BT synchronizes the receive data and control signals on the falling edge of RXC in order to stabilize the signals at the rising edge of the clock with 10ns setup and hold times. Transmit Enable: The MAC must assert TXEN at the same time as the first nibble of the preamble, and de-assert TXEN after the last bit of the packet. Receive Data Valid: The KS8721B/BT asserts RXDV when it receives a valid packet. Line operating speed and MII mode will determine timing changes in the following way: * For 100BaseTX link with the MII in 4B mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the data packet. * For 10BaseT links, the entire preamble is truncated. RXDV is asserted with the first nibble of the SFD " 5D" and remains asserted until the end of the packet. Error Signals: Whenever the KS8721B/BT receives an error symbol from the network, it asserts RXER and drives "1110" (4B) on the RXD pins. When the MAC asserts TXER, the KS8721B/BT will drive "H" symbols (a Transmit Error define in the IEEE 802.3 4B/5B code group) out on the line to force signaling errors. Carrier Sense (CRS): For 100TX links, a start-of-stream delimiter, or /J/K symbol pair causes assertion of Carrier Sense (CRS). An end-of-stream delimiter, or /T/R symbol pair causes de-assertion of CRS. The PMA layer will also de-assert CRS if IDLE symbols are received without /T/R, yet in this case RXER will be asserted for one clock cycle when CRS is de-asserted. For 10T links, CRS assertion is based on reception of valid preamble, and de-assertion on reception of an end-of-frame (EOF) marker. KS8721B/BT 12 August 2003 KS8721B/BT Micrel Collision: Whenever the line state is half-duplex and the transmitter and receiver are active at the same time, the KS8721B/ BT asserts its collision signal, which is asynchronous to any clock. RMII (Reduced MII) Data Interface RMII interface specifies a low pin count (Reduced) Media Independent Interface (RMII) intended for use between Ethernet PHYs and Switch or Repeater ASICs. It is fully compliant with IEEE 802.3u [2]. This interface has the following characteristics: * It is capable of supporting 10Mbps and 100Mbps data rates. * A single clock reference is sourced from the MAC to PHY (or from an external source). * It provides independent 2-bit wide (di-bit) transmit and receive data paths. * It uses TTL signal levels, compatible with common digital CMOS ASIC processes. RMII Signal Definition Signal Name REF_CLK CRS_DV RXD[1:0] TX_EN TXD[1:0] RX_ER Note 1. Direction (w/ respect to the PHY) Input Output Output Input Input Output Direction (w/ respect to the MAC) Input or Output Input Input Output Output Input (Not Required) Use Synchronous clock reference for receive, transmit and control interface Carrier Sense/Receive Data Valid Receive Data Transit Enable Transit Data Receive Error Unused MII signals, TXD[3:2], TXER need to tie to GND when RMII is using. Reference Clock (REF_CLK) REF_CLK is a continuous 50MHz clock that provides the timing reference for CRS_DV, RXD[1:0], TX_EN, TXD[1:0], and RX_E. REF_CLK is sourced by the MAC or an external source. Switch implementations may choose to provide REF_CLK as an input or an output depending on whether they provide a REF_CLK output or rely on an external clock distribution device. Each PHY device shall have an input corresponding to this clock but may use a single clock input for multiple PHYs implemented on a single IC. Carrier Sense/Receive Data Valid (CRS_DV) CRS_DV is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. That is, in 10BASE-T mode, when squelch is passed or in 100BASE-X mode when 2 non-contiguous zeroes in 10 bits are detected carrier is said to be detected. Loss of carrier shall result in the de-assertion of CRS_DV synchronous to REF_CLK. So long as carrier criteria are being met, CRS_DV shall remain asserted continuously from the first recovered di-bit of the frame through the final recovered di-bit and shall be negated prior to the first REF_CLK that follows the final di-bit. The data on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchronous relative to REF_CLK, the data on RXD[1:0] shall be "00" until proper receive signal decoding takes place (see definition of RXD[1:0] behavior). Receive Data [1:0] (RXD[1:0]) RXD[1:0] shall transition synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] transfers two bits of recovered data from the PHY. In some cases (e.g. before data recovery or during error conditions) a pre-determined value for RXD[1:0] is transferred instead of recovered data. RXD[1:0] shall be "00" to indicate idle when CRS_DV is deasserted. Values of RXD[1:0] other than "00" when CRS_DV is de-asserted are reserved for out-of-band signalling (to be defined). Values other than "00" on RXD[1:0] while CRS_DV is de-asserted shall be ignored by the MAC/repeater. Upon assertion of CRS_DV, the PHY shall ensure that RXD[1:0]=00 until proper receive decoding takes place. Transmit Enable (TX_EN) Transmit Enable TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] on the RMII for trans-mission. TX_EN shall be asserted synchronously with the first nibble of the preamble and shall remain asserted while all di-bits to be transmitted are presented to the RMII. TX_EN shall be negated prior to the first REF_CLK following the final di-bit of a frame. TX_EN shall transition synchronously with respect to REF_CLK. August 2003 13 KS8721B/BT KS8721B/BT Micrel Transmit Data [1:0] (TXD[1:0]) Transmit Data TXD[1:0] shall transition synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are accepted for transmission by the PHY. TXD[1:0] shall be "00" to indicate idle when TX_EN is de-asserted. Values of TXD[1:0] other than "00" when TX_EN is de-asserted are reserved for out-of-band signalling (to be defined). Values other than "00" on TXD[1:0] while TX_EN is deasserted shall be ignored by the PHY. Collision Detection Since the definition of CRS_DV and TX_EN both contain an accurate indication of the start of frame, the MAC can reliably regenerate the COL signal of the MII by ANDing TX_EN and CRS_DV. During the IPG time following the successful transmission of a frame, the COL signal is asserted by some transceivers as a self-test. The Signal Quality Error (SQE) function will not be supported by the reduced MII due to the lack of the COL signal. Historically, SQE was present to indicate that a transceiver located physically remote from the MAC was functioning. Since the reduced MII only supports chip-to-chip connections on a PCB, SQE functionality is not required. RX_ER The PHY shall provide RX_ER as an output according to the rules specified in IEEE 802.3u [2] (see Clause 24, Figure 24-11 - Receive State Diagram). RX_ER shall be asserted for one or more REF_CLK periods to indicate that an error (e.g. a coding error or any error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sublayer) was detected somewhere in the frame presently being transferred from the PHY. RX_ER shall transition synchronously with respect to REF_CLK. While CRS_DV is de-asserted, RX_ER shall have no effect on the MAC. RMII AC Characteristics Symbol Parameter REF_CLK Frequency REF_CLK Duty Cycle tSU tH TXD[1:0]. TX_EN, RXD[1:0], CRS_DV, RX_ER Data Set-Up to REF_CLK Rising TXD[1:0]. TX_EN, RXD[1:0], CRS_DV, RXER Data Hold from REF_CLK Rising Edge 35 4 2 Min Typ 50 65 Max Units MHz % ns ns KS8721B/BT 14 August 2003 KS8721B/BT Micrel Auto Crossover (Auto MDI/MDI-X) Automatic MDI/MDI-X configuration is intended to eliminate the need for crossover cables between similar devices. The assignment of pin-outs for a 10/100 BASE-T crossover function cable is shown below. This feature can eliminate the confusion in real applications so both straight cable and crossover cable can be used. This feature is controlled by register 1f:13. See "Register 1fh-100BaseTX PHY Controller" section for details. 10/100 Base-T Media Dependent Interface 10/100 Base-T Media Dependent Interface 1 1 Transmit Pair 2 3 4 2 3 4 Receive Pair Receive Pair 5 6 7 8 5 6 7 8 Transmit Pair Modular Connector (RJ45) NIC Modular Connector (RJ45) HUB (Repeater or Switch) Figure 1. Straight Through Cable 10/100 BASE-T Media Dependent Interface 10/100 Base-T Media Dependent Interface 1 1 Receive Pair 2 3 4 2 3 4 Receive Pair Transmit Pair 5 6 7 8 5 6 7 8 Transmit Pair Modular Connector (RJ45) HUB (Repeater or Switch) Modular Connector (RJ45) HUB (Repeater or Switch) Figure 2. Crossover Cable August 2003 15 KS8721B/BT KS8721B/BT Micrel Power Management The KS8721B/BT offers the following modes for power management: * Power Down Mode: This mode can be achieved by writing to Register 0.11 or pulling pin 30 PD# Low. * Power Saving Mode: This mode can be disabled by writing to Register 1fh.10. The KS8721B/BT will then turn off everything except for the Energy Detect and PLL circuits when the cable is not installed. In other words, the KS8721B/BT will shutdown most of the internal circuits to save power if there is no link. Power saving mode will be in his most effective state when auto-negotiation mode is enable. 100BT FX Mode 100BT FX mode is activated when FXSD/FXEN is higher 0.6V (This pin has a default pull down). Under this mode, the autonegotiation and auto-MDIX features are disabled. In fiber operation FXSD pin should connect to the SD (signal detect) output of the fiber module. The internal threshold of FXSD is around 1/2 VDD 50mV (1.25V 0.05V). Above this level, it is considered fiber signal detected, and the operation is summarized in the following table: FXSD/FXEN Less than 0.6V Less than 1.25V, but greater than 0.6V Greater than 1.25 Condition 100TX mode FX mode No signal detected FEF generated FX mode signal detected Table 1. 100BT FX Mode To ensure a proper operation, the swing of fiber module SD should cover the threshold variation. A resistive voltage divider is recommended to adjust the SD voltage range. FEF (Far End Fault), repetition of a special pattern which consists of 84-one and 1-zero, is generated under "FX mode with no signal detected." The purpose of FEF is to notify the sender of a faulty link. When receiving a FEF, the LINK will go down to indicate a fault, even with fiber signal detected. The transmitter does not affect by receiving a FEF and still sends out its normal transmit pattern from MAC. FEF can be disabled by strapping pin 27 low. Refer to "Strapping Options" section. Media Converter Operation KS8721B/BT is capable of performing media conversion with 2 parts in a back to back RMII loop-back mode as indicated in the diagram. Both parts are in RMII mode and with RMII BTB asserted (pin 21 and 22 strapped high). One part is operating at TX mode and the other in FX mode. Both parts can share a common 50MHz oscillator. Under this operation, auto-negotiation on the TX side will prohibit 10baseT link up. TXD2, active High, can disable transmitter and set it at tri-state. RXD2 serves as energy detection can indicate if there is line signal detected. TXD3 should tied low and RXD3 let float. Please contact Micrel FAE for Application Note. Vcc Rx +/- 21 22 Pin RxD TxD KS8721B Tx +/TxC/ Ref_CLK OSC TxC/ Ref_CLK TxD RxD Pin 34 Pin 21 22 50 MHz FTx KS8721B (Fiber Mode) FRx Vcc To the SD pin of the Fiber Module Figure 3. Fiber Module KS8721B/BT 16 August 2003 KS8721B/BT Micrel Register Map Register No. 0h 1h 2h 3h 4h 5h 6h 7h 8h 15h 1bh 1fh Description Basic Control Register Basic Status Register PHY Identifier I PHY Identifier II Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register Auto-Negotiation Next Page Register Link Partner Next Page Ability RXER Counter Register Interrupt Control/Status Register 100BaseTX PHY Control Register Address Name Description Mode(Note 1) Default Register 0h - Basic Control 0.15 0.14 0.13 0.12 0.11 0.10 0.9 0.8 0.7 0.6:1 0.0 Reset Loop-back Speed Select (LSB) Auto-Negotiation Enable Power Down Isolate Restart Auto-Negotiation Duplex Mode Collision Test Reserved Disable Transmitter 0 = enable transmitter 1 = disable transmitter 1 = software reset. Bit is self-clearing 1 = loop-back mode; 0 = normal operation 1 = 100Mbps; 0 = 10Mbps Ignored if Auto-Negotiation is enabled (0.12 = 1) 1 = enable auto-negotiation process (override 0.13 and 0.8) 0 = disable auto-negotiation process 1 = power down mode; 0 = normal operation 1 = electrical isolation of PHY from MII and TX+/TX0 = normal operation 1 = restart auto-negotiation process 0 = normal operation. Bit is self-clearing 1 = full duplex; 0 = half duplex 1 = enable COL test; 0 = disable COL test RW/SC RW RW RW RW RW RW/SC RW RW RO R/W 0 0 Set by SPD100 Set by NWAYEN 0 Set by ISO 0 Set by DUPLEX 0 0 0 Register 1h - Basic Status 1.15 1.14 1.13 1.12 1.11 Note 1. 100BaseT4 100BaseTX Full Duplex 100BaseTX Half Duplex 10BaseT Full Duplex 10BaseT Half Duplex 1 = T4 capable; 0 = not T4 capable 1 = capable of 100BaseX full duplex 0 = not capable of 100BaseX full duplex 1 = capable of 100BaseX half duplex 0 = not capable of 100BaseX half duplex 1 = 10Mbps with full duplex 0 = no 10Mbps with full duplex capability 1 = 10Mbps with half duplex 0 = no 10Mbps with half duplex capability RO RO RO RO RO 0 1 1 1 1 RW: Read/Write, RO: Read only, SC: Self clear, LH: Latch High, LL: Latch Low. Some of the default values are set by strap-in. See "Srapping Options." August 2003 17 KS8721B/BT KS8721B/BT Address 1.10:7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 Name Reserved No Preamble Auto-Negotiation Complete Remote Fault Auto-Negotiation Ability Link Status Jabber Detect Extended Capability 1 = preamble suppression; 0 = normal preamble 1 = auto-negotiation process completed 0 = auto-negotiation process not completed 1 = remote fault; 0 = no remote fault 1 = capable to perform auto-negotiation 0 = unable to perform auto-negotiation 1 = link is up; 0 = link is down Description Mode(Note 1) RO RO RO RO/LH RO RO/LL Default 0 1 0 0 1 0 0 1 Micrel 1 = jabber detected; 0 = jabber not detected. Default is Low RO/LH 1 = supports extended capabilities registers RO Register 2h - PHY Identifier 1 2.15:0 PHY ID Number Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier (OUI). Micrel's OUI is 0010A1 (hex) RO 0022h Register 3h - PHY Identifier 2 3.15:10 3.9:4 3.3:0 PHY ID Number Model Number Revision Number Assigned to the 19th through 24th bits of the Organizationally RO Unique Identifier (OUI). Micrel's OUI is 0010A1 (hex) Six bit manufacturer's model number Four bit manufacturer's model number RO RO 000101 100001 1001 Register 4h - Auto-Negotiation Advertisement 4.15 4.14 4.13 4.12 : 11 4.10 4.9 4.8 Next Page Reserved Remote Fault Reserved Pause 100BaseT4 100BaseTX Full Duplex 1 = pause function supported; 0 = no pause function 1 = T4 capable; 0 = no T4 capability 1 = TX with full duplex; 0 = no TX full duplex capability 1 = remote fault supported; 0 = no remote fault 1 = next page capable; 0 = no next page capability. RW RO RW RO RW RO RW 0 0 0 0 0 0 Set by SPD100 & DUPLEX Set by SPD100 Set by DUPLEX 1 00001 4.7 4.6 4.5 4.4:0 100BaseTX 10BaseT Full Duplex 10BaseT Selector Field 1 = TX capable; 0 = no TX capability 1 = 10Mbps with full duplex 0 = no 10Mbps full duplex capability 1 = 10Mbps capable; 0 = no 10Mbps capability [00001] = IEEE 802.3 RW RW RW RW Register 5h - Auto-Negotiation Link Partner Ability 5.15 5.14 5.13 5.12 Note 1. Next Page Acknowledge Remote Fault Reserved 1 = next page capable; 0 = no next page capability 1 = link code word received from partner 0 = link code word not yet received 1 = remote fault detected; 0 = no remote fault RO RO RO RO 0 0 0 0 RW: Read/Write, RO: Read only, SC: Self clear, LH: Latch High, LL: Latch Low. Some of the default values are set by strap-in. See "Srapping Options." KS8721B/BT 18 August 2003 KS8721B/BT Address 5.11:10 Name Pause Description 5.10 5 .11 00 No PAUSE 01 Asymmetric PAUSE (link partner) 10 Symmetric PAUSE 11 Symmetric & Asymmetric PAUSE (local device) 1 = T4 capable; 0 = no T4 capability 1 = TX with full duplex; 0 = no TX full duplex capability 1 = TX capable; 0 = no TX capability 1 = 10Mbps with full duplex 0 = no 10Mbps full duplex capability 1 = 10Mbps capable; 0 = no 10Mbps capability [00001] = IEEE 802.3 Mode(Note 1) RO Default 0 Micrel 5.9 5.8 5.7 5.6 5.5 5.4:0 100 BaseT4 100BaseTX Full Duplex 100BaseTX 10BaseT Full Duplex 10BaseT Selector Field RO RO RO RO RO RO 0 0 0 0 0 00001 Register 6h - Auto-Negotiation Expansion 6.15:5 6.4 6.3 6.2 6.1 6.0 Reserved Parallel Detection Fault Link Partner Next Page Able Next Page Able Page Received Link Partner Auto-Negotiation Able 1 = fault detected by parallel detection 0 = no fault detected by parallel detection. 1 = link partner has next page capability 0 = link partner does not have next page capability 1 = local device has next page capability 0 = local device does not have next page capability 1 = new page received; 0 = new page not yet received 1 = link partner has auto-negotiation capability 0 = link partner does not have auto-negotiation capability RO RO/LH RO RO RO/LH RO 0 0 0 1 0 0 Register 7h - Auto-Negotiation Next Page 7.15 7.14 7.13 7.12 7.11 7.10:0 Next Page Reserved Message Page Acknowledge2 Toggle Message Field 1 = message page; 0 = unformatted page 1 = will comply with message 0 = cannot comply with message 1 = previous value of the transmitted link code word equaled logic One; 0 = logic Zero 11-bit wide field to encode 2048 messages 1 = additional next page(s) will follow; 0 = last page RW RO RW RW RO RW 0 0 1 0 0 001 Register 8h - Link Partner Next Page Ability 8.15 8.14 8.13 8.12 8.11 Next Page Acknowledge Message Page Acknowledge2 Toggle 1 = additional Next Page(s) will follow; 0 = last page 1 = successful receipt of link word 0 = no successful receipt of link word 1 = Message Page; 0 = Unformatted Page 1 = able to act on the information 0 = not able to act on the information 1 = previous value of transmitted Link Code Word equal to logic zero; 0 = previous value of transmitted Link Code Word equal to logic one RO RO RO RO RO 0 0 0 0 0 8.10:0 Note 1. Message Field RO 0 RW: Read/Write, RO: Read only, SC: Self clear, LH: Latch High, LL: Latch Low. Some of the default values are set by strap-in. See "Srapping Options." August 2003 19 KS8721B/BT KS8721B/BT Address Name Description Mode(Note 1) Default Micrel Register 15h - RXER Counter 15.15:0 RXER Counter RX Error counter for the RX_ER in each package RO 0000 Register 1bh - Interrupt Control/Status Register 1b.15 1b.14 1b.13 1b.12 1b.11 1b.10 1b.9 1b.8 1b.7 1b.6 1b.5 1b.4 1b.3 1b.2 1b.1 1b.0 Jabber Interrupt Enable Receive Error Interrupt Enable Page Received Interrupt Enable Parallel Detect Fault Interrupt Enable Link Partner Acknowledge Interrupt Enable Link Down Interrupt Enable Remote Fault Interrupt Enable Link Up Interrupt Enable Jabber Interrupt Receive Error Interrupt Page Receive Interrupt Parallel Detect Fault Interrupt Link Partner Acknowledge Interrupt Link Down Interrupt Remote Fault Interrupt Link Up Interrupt 1 = Enable Jabber Interrupt; 0=Disable Jabber Interrupt 1 = Enable Receive Error Interrupt 0 = Disable Receive Error Interrupt 1 = Enable Page Received Interrupt 0 = Disable Page Received Interrupt 1 = Enable Parallel Detect Fault Interrupt 0 = Disable Parallel Detect Fault Interrupt 1 = Enable Link Partner Acknowledge Interrupt 0 = Disable Link Partner Acknowledge Interrupt 1 = Enable Link Down Interrupt 0 = Disable Link Down Interrupt 1 = Enable Remote Fault Interrupt 0 = Disable Remote Fault Interrupt 1 = Enable Link Up Interrupt 0 = Disable Link Up Interrupt 1 = Jabber Interrupt Occurred 0 = Jabber Interrupt Does Not Occurred 1 = Receive Error Occurred 0 = Receive Error Does Not Occurred 1 = Page Receive Occurred 0 = Page Receive Does Not Occurred 1 = Parallel Detect Fault Occurred 0 = Parallel Detect Fault Does Not Occurred 1 = Link Partner Acknowledge Occurred 0 = Link Partner Acknowledge Does Not Occurred 1 = Link Down Occurred 0 = Link Down Does Not Occurred 1 = Remote Fault Occurred 0 = Remote Fault Does Not Occurred 1 = Link Up Interrupt Occurred 0 = Link Up Interrupt Does Not Occurred RW RW RW RW RW RW RW RW RO RO RO RO RO RO RO RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register 1fh - 100BaseTX PHY Controller 1f.15:14 1f:13 1f.12 1f.11 Reserved Pairswap Disable Energy Detect Force Link 1 = Disable MDI/MDIX; 0 = Enable MDI/MDIX 1 = Presence of Signal on RX+/- Analog Wire Pair 0 = No Signal Setected on RX+/1 = Force Link Pass; 0 = Normal Link Operation This bit bypasses the control logic and allow transmitter to send pattern even if there is no link. 1 = Enable Ppower Saving; 0 = Disable 1 = Interrupt Pin Active High; 0 = Active Low 1 = Enable Jabber Counter; 0 = Disable 1 = Auto-Negotiation Complete; 0 = Not Nomplete R/W RO R/W 0 0 0 1f.10 1f.9 1f.8 1f.7 Note 1. Power Saving Interrupt Level Enable Jabber Auto-Negotiation Complete RW RW RW RW 1 0 1 0 RW: Read/Write, RO: Read only, SC: Self clear, LH: Latch High, LL: Latch Low. Some of the default values are set by strap-in. See "Srapping Options." KS8721B/BT 20 August 2003 KS8721B/BT Address 1f.6 1f.5 1f.4:2 Name Enable Pause (Flow-Control Result) PHY Isolate Description 1 = flow control capable; 0 = no flow control 1 = PHY in isolate mode; 0 = not isolated Mode(Note 1) RO RO RO Default 0 0 0 Micrel Operation Mode Indication [000] = still in auto-negotiation [001] = 10BaseT half duplex [010] = 100BaseTX half duplex [011] = default [101] = 10BaseT full duplex [110] = 100BaseTX full duplex [111] = PHY/MII isolate Enable SQE Test Disable Data Scrambling 1 = enable SQE test; 0 = disable 1 = disable scrambler; 0 = enable 1f.1 1f.0 Note 1. RW RW 0 0 RW: Read/Write, RO: Read only, SC: Self clear, LH: Latch High, LL: Latch Low. Some of the default values are set by strap-in. See "Srapping Options." August 2003 21 KS8721B/BT KS8721B/BT Micrel Absolute Maximum Ratings (Note 1) Supply Voltage (VDDC, VDD_PLL, VDD_TX, VDD_RCV, VDD_RX) ................................................... -0.5V to +3.0V (VDDIO) .................................................... -0.5V to +4.0V Input Voltage ............................................... -0.5V to +4.0V Output Voltage ............................................ -0.5V to +4.0V Lead Temperature (soldering, 10 sec.) ..................... 270C Storage Temperature (TS) ....................... -55C to +150C Operating Ratings (Note 2) Supply Voltage (VDDC, VDD_PLL, VDD_TX, VDD_RCV, VDD_RX) ........................................... +2.375V to +2.625V (VDDIO) ............... +2.375V to +2.625V or +3.0V to +3.6V Ambient Temperature (TA) ........................... -0C to +70C Package Thermal Resistance (Note 3) TQFP (JA) ..................................................... 69.64C/W SSOP (JA) ..................................................... 42.91C/W Electrical Characteristics (Note 4) VDD = 2.5V 5%; TA = 0C to +70C; unless noted; bold values indicate -40C TA +85C; unless noted. Symbol Parameter Condition Min Typ Max Units Total Supply Current (including TX output driver current) IDD1 IDD2 IDD3 IDD5 TTL Inputs VIH VIL IIN TTL Outputs VOH VOL |IOZ| RIN Output High Voltage Output Low Voltage Output Tr-State Leakage IOH = -4mA IOL = 4mA VDD (I/O) -0.4 0.4 10 V V A Input High Voltage Input Low Voltage Input Current VIN = GND ~ VDD -10 VDD (I/O) -0.8 0.8 10 V V A Normal 100BaseTX Normal 10BaseT (50% utilization) Power Saving Mode 100BaseTX Power Down Mode 110 150 40 5 130 180 60 mA mA mA mA 100BaseTX Receive RX+/RX- Differential Input Resistance Propagation Delay from magnetics to RDTX 8 50 110 k ns 100BaseTX Transmit (measured differentially after 1:1 transformer) VO VIMB tr, tt Peak Differential Output Voltage Output Voltage Imbalance Rise/Fall Time Rise/Fall Time Imbalance 50 from each output to VDD 50 from each output to VDD 3 0 0.95 1.05 2 5 0.5 0.5 5 0.75 from TDTX to magentics 45 0.7 60 1.4 V % ns ns 100BaseTX Transmit (measured differentially after 1:1 transformer) Duty Cycle Distortion Overshoot VSET Reference Voltage of ISET Propagation Delay Jitters Note 1. Note 2. Note 3. Note 4. Exceeding the absolute maximum rating may damage the device. The device is not guaranteed to function outside its operating rating. Unused inputs must always be tied to an appropriate logic voltage level (Ground to VDD). No HS (heat spreader) in package. Specification for packaged product only. V % ns ns ns(pk-pk KS8721B/BT 22 August 2003 KS8721B/BT Symbol Parameter Condition Min Typ Max Micrel Units 10BaseTX Receive RIN VSQ VP tr, tt X1, X2 RXC100 RXC10 TXC100 TXC10 RX+/RX- Differential Input Resistance Squelch Threshold 5MHz square wave 8 400 k mV 10BaseTX Transmit (measured differentially after 1:1 transformer) Peak Differential Output Voltage Jitters Added Rise/Fall Time 50 from each output to VDD 50 from each output to VDD 25 2.2 2.8 3.5 V ns ns Clock Outputs Crystal Oscillator Receive Clock, 100TX Receive Clock, 10T Receive Clock Jitters Transmit Clock, 100TX Transmit Clock, 10T Transmit Clock Jitters 25 25 2.5 3.0 25 2.5 1.8 MHZ MHZ MHZ ns(pk-pk) MHZ MHZ ns(pk-pk) August 2003 23 KS8721B/BT KS8721B/BT Micrel Timing Diagrams TXC tHD2 tSU2 tSU1 tCRS1 tCRS2 tLAT Valid Data TXEN tHD1 TXD[3:0] CRS TXP/TXM SQE Timing TXC TXEN COL tSQE tSQEP Figure 4. 10BaseT MII Transmit Timing Symbol tSU1 tSU2 tHD1 tHD2 tCRS1 tCRS2 tLAT tSQE tSQEP Parameter TXD [3:0] Set-Up to TXC High TXEN Set-Up to TXC High TXD [3:0] Hold After TXC High TXEN Hold After TXC High TXEN High to CRS Asserted Latency TXEN Low to CRS De-Asserted Latency TXEN High to TXP/TXM Output (TX Latency) COL (SQE) Delay Aftter TXEN Ae-Asserted COL (SQE) Pulse Duration Min 10 10 0 0 Typ Max Units ns ns ns ns 4 8 4 2.5 1.0 BT BT BT s s Table 2. 10BaseT MII Transmit Timing Parameters KS8721B/BT 24 August 2003 KS8721B/BT Micrel TXC tSU2 TXEN tHD2 tHD1 tSU1 TXD[3:0], TXER Data In tCRS2 CRS tCRS1 tLAT TX+/TX- Symbol Out Figure 5. 100BaseT MII Transmit Timing Symbol tSU1 tSU2 tHD1 tHD2 tHD3 tCRS1 tCRS2 tLAT Parameter TXD [3:0] Set-Up to TXC High TXEN Set-Up to TXC High TXD [3:0] Hold After TXC High TXER Hold After TXC High TXEN Hold After TXC High TXEN High to CRS Asserted Latency TXEN Low to CRS De-Asserted Latency TXEN High to TX+/TX- Output (TX Latency) Min 10 10 0 0 0 Typ Max Units ns ns ns ns ns 4 4 7 BT BT BT Table 3. 100BaseT MII Transmit Timing Parameters August 2003 25 KS8721B/BT KS8721B/BT Micrel RX+/RX- Start of Stream End of Stream CRS tCRS1 tCRS2 tRLAT tHD RXDV RXD[3:0] RXER tSU RXC tWH tWL tP Figure 6. 100BaseT MII Receivce Timing Symbol tP tWL tWH tSU tHD tRLAT tCRS1 tCRS2 Parameter RXC Period RXC Pulse Width RXC Pulse Width RXD [3:0], RXER, RXDV Set-Up to Rising Edge of RXC RXD [3:0], RXER, RXDV Hold from Rising Edge of RXC CRS to RXD Latency, 4B or 5B Aligned "Start of Stream" to CSR Asserted "End of Stream" to CSR De-Asserted Min Typ 40 Max Units ns ns ns 20 20 20 20 1 2 140 170 3 ns ns BT ns ns Table 4. 100BaseT MII Receive Timing Parameters KS8721B/BT 26 August 2003 KS8721B/BT Micrel FLP Burst FLP Burst TX+/TX- tFLPW tBTB Clock Pulse TX+/TX- Data Pulse Clock Pulse Data Pulse tPW tCTD tPW tCTC Figure 7. Auto-Negotiation/Fast Link Pulse Timing Symbol tBTB tFLPW tPW tCTD tCTC Parameter FLP Burst to FLP Burst FLP Burst Width Clock/Data Pulse Width Clock Pulse to Data Pulse Clock Pulse to Clock Pulse Number of Clock/Data Pulses per Burst Min 8 Typ 16 2 100 69 136 Max 24 Units ms ms ns s s s 17 33 Table 5. Auto-Negotiation/Fast Link Pulse Timing August 2003 27 KS8721B/BT KS8721B/BT Micrel tP MDC tMD1 MDIO (Into Chip) tMD2 Valid Data Valid Data tMD3 MDIO (Out of Chip) Valid Data Figure 8. Serial Management Interface Timing Symbol tP tMD1 tMD2 tMD3 Parameter MDC Period MDIO Set-Up to MDC (MDIO as input) MDIO Hold after MDC (MDIO as input) MDC to MDIO Valid (MDIO as output) Min Typ 400 Max Units ns ns ns 10 10 222 ns Table 6. Serial Management Interface Timing KS8721B/BT 28 August 2003 KS8721B/BT Micrel Supply Voltage tsr RST_N tcs tch Strap-In Value trc Strap-In / Output Pin Figure 9. Reset Timing Symbol tsr tcs tch trc Parameter Stable Supply Voltages to Reset High Configuration Set-Up Time Configuration Hold Time Reset to Strap-In Pin Output Min 10 50 50 50 Typ Max Units ms ns ns s Table 7. Reset Timing Parameters August 2003 29 KS8721B/BT KS8721B/BT Micrel Selection of Isolation Transformer(Note 1) One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Characteristics Name Turns Ratio Open-Circuit Inductance (min.) Leakage Inductance (max.) Inter-Winding Capacitance (max.) D.C. Resistance (max.) Insertion Loss (max.) HIPOT (min.) Note 1. Value 1 CT : 1 CT 350H 0.4H 12pF 0.9 1.0dB 1500Vrms Test Condition 100mV, 100 KHz, 8 mA 1MHz (min.) 0MHz to 65MHz The IEEE 802.3u standard for 100BaseTX assumes a transformer loss of 0.5dB. For the transmit line transformer, insertion loss of up to 1.3dB can be compensated by increasing the line drive current by means of reducing the ISET resistor value. Selection of Reference Crystal An oscillator or crystal with the following typical characteristics is recommended. Characteristics Name Frequency Frequency Tolerance (max.) Load Capacitance (max.) Series Resistance (max.) Value 25.00000 100 20 25 Units MHz ppm pF Single Port Magnetic Manufacturer Pulse Bel Fuse YCL Transpower Delta LanKom Part Number H1102 S558-5999-U7 PT163020 HB726 LF8505 LF-H41S Auto MDIX Yes Yes Yes Yes Yes Yes Number of Ports 1 1 1 1 1 1 Table 8. Qualified Transformer Lists KS8721B/BT 30 August 2003 KS8721B/BT Micrel Package Information 48-Pin SSOP (SM) August 2003 31 KS8721B/BT KS8721B/BT Micrel 48-Pin TQFP (TQ) MICREL, INC. 1849 FORTUNE DRIVE SAN JOSE, CA 95131 TEL USA + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2003 Micrel, Incorporated. KS8721B/BT 32 August 2003 |
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